1. Field of the Invention
The present invention relates to a method of arranging alignment marks. It particularly relates to a method of arranging alignment marks capable of reducing the region other than a device region for forming therein a semiconductor device by shifting the positions of a pair of adjacent alignment marks, in achieving highly precise alignment with the use of four alignment marks.
2. Description of the Background Art
Recently, in the exposure step of the process for manufacturing semiconductor memory devices or the like, alignment of a stepper has becomes important for precise fine-patterning process. While various stepper alignment methods have been conventionally proposed, an alignment method using four alignment marks is disclosed, for example, in Japanese Patent Laying-Open No. 6-349705. In achieving alignment using such four alignment marks, the four alignment marks are formed at positions which are in point symmetry with respect to the center of a shot region for the stepper. Then, the positions of the four alignment marks are detected to correct the offsets between the detected positions and the coordinates of preset positions. The alignment marks are preferably arranged at four corners of the shot region.
FIG. 4A shows an example of a conventional arrangement method for alignment marks 4a, 4b, 4c, and 4d. Referring to FIG. 4A, a dicing region 2 provided for dicing and a TEG (Test Element Group) region 5 are provided around a device region 3 for forming a semiconductor device therein. When the device region 3 is thus surrounded by dicing region 2 and TEG region 5, alignment marks 4a-4d are generally arranged within dicing region 2 or TEG region 5. Such provision of four alignment marks 4a-4d allows highly precise alignment as described above.
However, while highly precise alignment as described above is sought for, so is increase in the number of the devices manufactured per wafer. One technique for increasing the number of the devices manufactured per wafer is to reduce the region other than device region 3.
In FIG. 4B, TEG region 5 is simply removed in order to reduce the region other than device region 3. As shown in FIG. 4B, when TEG region 5 is simply removed, positions for forming alignment marks 4a and 4d are not ensured. Thus, it is not ensured that four alignment marks are provided within shot region 1, making it difficult to achieve precise alignment.
Thus, it has been difficult to increase the number of the devices manufactured per wafer without degrading precision of alignment.